Graduate student Sheldon A. Taylor, Master of Science in Engineering, will be presenting his project called: Implementation of Static Asynchronous NCL Threshold Gates and Static Logic Gates: GNRFET vs. CMOS Technology.
- Date: Monday, Nov. 28
- Time: 12:30-2 p.m.
- Where: Microsoft Teams, join here
Here’s an abstract of the project:
The Si-CMOS-based synchronous domain has been dominating digital design for quite some time. However, as devices scale down into the deep submicron region, traditional Si-CMOS technology has reached a point where further advancement in terms of speed and size is becoming extremely challenging. Along with the scaling limitations, high-speed clock management also adds to the design complexity. Null Convention logic (NCL), one of the main QDI paradigms, is a clockless approach; thus, it eliminates the clock-related issues faced in the synchronous domain. Graphene Nano-Ribbon Field Effect Transistor (GNRFET) is an emerging technology that has received a lot of attention in recent years due to its high carrier mobility for ballistic transport, compatibility with high k dielectrics, high carrier velocity to have abrupt switching, and good thermal conductivity. In this work, various GNRFET-based implementations of static NCL threshold gates and conventional two-input digital logic gates are presented. The different gate designs are analyzed in terms of speed of operation, leakage power dissipation, and energy consumption. The results are then compared to the Si-CMOS implementations of these gates at the same future size and nominal voltage.